Memory architecture - PDFSEARCH.IO - Document Search Engine

Memory architecture
Results: 1714

#	Item
761	Title (Verdana Bold 18pt) Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-28 00:17:42 CPU cache Cache Central processing unit Computer memory X86 Computer architecture Computer hardware Computing
762	ARM810: Dancing to the Beat of a Different Drum Guy Larri 90 Fulbourn Road, Cherry Hinton, Cambridge, CB1 4JN, England Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:47:39 Computer memory CPU cache Cache R8000 Classic RISC pipeline Computer hardware Central processing unit Computer architecture
763	Hummingbird: A Low-Cost Superscalar PA-RISC Processor Stephen Undy Hewlett-Packard Hot Chips V Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 22:45:25 Computer memory Instruction set architectures Central processing unit CPU cache Cache PA-RISC Reduced instruction set computing Hewlett-Packard Dynamic random-access memory Computer hardware Computing Computer architecture
764	Level-3 BLAS on Myriad Multi-Core Media-Processor SoC 1 Tomasz Szydzik 1 Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2014-08-04 15:33:27 Numerical linear algebra Numerical software Computer memory Embedded microprocessors Central processing unit General Matrix Multiply LEON Direct memory access CPU cache Computer hardware Computer architecture Computing
765	TheLadders CUSTOMER SUCCESS STORY Ladders, a leading job site chose ClustrixDB to eliminate several problems: 1) the need to shard data, 2) master database single point of failure, 3) a single box memory Add to Reading List Source URL: www.clustrix.com Language: English - Date: 2014-06-18 15:26:44 Relational database management systems Cross-platform software MySQL Computer storage SQL Shard Database Shared nothing architecture Scalability Data management Computing Database management systems
766	proAptiv: Efficient Performance on a Fully-Synthesizable Core 28 August 2012 Ranganathan “Suds” Sudhakar Chief Architect Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-28 00:24:44 Computing MIPS architecture Central processing unit Computer memory CPU cache FLOPS Computer architecture Computer hardware MIPS Technologies
767	Power Edge of Network(tm) Processor Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-28 00:16:01 Computer memory CPU cache Computing PowerPC 400 QorIQ Computer hardware Computer architecture PowerPC A2
768	Sitara Linux Boot Process Add to Reading List Source URL: events.linuxfoundation.org Language: English - Date: 2015-03-25 01:23:13 Electronics Computer memory Embedded systems Computer buses Instruction set architectures CPU cache Microcontroller General Purpose Input/Output ARM architecture Computer architecture Central processing unit Computer hardware
769	1 SPARC T5: 16-core CMT Processor with Glueless 1-Hop Scaling to 8-Sockets 2 Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-28 00:27:15 CPU cache Cache Central processing unit SPARC Sandy Bridge SPARC T3 UltraSPARC T1 Computer hardware Computer architecture Computer memory
770	Large Scale Distributed Deep Networks Jeffrey Dean, Greg S. Corrado, Rajat Monga, Kai Chen, Matthieu Devin, Quoc V. Le, Mark Z. Mao, Marc’Aurelio Ranzato, Andrew Senior, Paul Tucker, Ke Yang, Andrew Y. Ng {jeff, gcorr Add to Reading List Source URL: www.cs.toronto.edu Language: English - Date: 2012-11-13 14:54:36 Computational statistics Applied mathematics Mathematics Econometrics Network architecture Supervised learning Stochastic gradient descent Limited-memory BFGS Mathematical optimization Neural networks Statistics Computational neuroscience

UPDATE